High speed operational amplifiers (op amps) are required to have high slew rates so that the full power bandwidth is higher and as a consequence lower distortion is achieved at higher frequencies and/or higher signal amplitudes. Unfortunately, current solutions increase full power bandwidth by sacrificing noise performance in the amplifier thus limiting the resolution of the output signal.
An example of such a solution is the widely known class AB input stage shown at 10 in FIG. 1. The input stage 12 is fast, but its noise performance is not as good when compared to single differential pair inputs. The reason for this is the amount of transistors that are required at the input, shown at transistors Q1 to Q8. Lower noise can be achieved in this input stage 12, but at the expense of quiescent current or more general power.
An alternative solution is shown in FIG. 2 at 20 and uses a dynamic biasing scheme that provides extra current to a differential pair in a folded cascode input stage, the teachings of which are incorporated herein by reference. This circuit 20 accomplishes the task of having higher full power bandwidth without sacrificing noise performance and power in the amplifier. In this design the amount of current available during a high slew signal is limited by the active loads feeding the folded part of the circuit, shown at transistors Q82 and Q62. These two transistors run out of VCE during a fast signal and therefore they will enter in the saturation region, decreasing the linearity of the amplifier.
This limitation calls for a new dynamically biased circuit that does not suffer from saturation during high slew signals and yet maintains low noise operation without trading off power.